The I2C interface (inter-integrated circuit) uses two bidirectional lines in order to provide communication between one or multiple masters and one or multiple slaves. The two aforementioned lines, the serial data line (SDA) and the serial clock line (SCL), are used to send data and to display the beginning and an end of transactions on the interface or on the bus. A beginning and an end of the transaction are designated as “START” and “STOP”. Every slave device on the I2C bus must have a device which detects the START/STOP states and/or sends and/or receives data.
However, the slave device must also distinguish between correct and incorrect transactions and is only permitted to respond to correct transactions. Although the aforementioned illegal transfers do not conform to the I2C specification, they are often used by various microcomputer devices on the market in order to reset all devices on the I2C bus.
Circuits which are already believed to be understood, which are discussed, for example, in U.S. Pat. No. 6,530,029 or CN 202600693, have problems with the aforementioned transfers which do not conform to the standard and may result in states in which the device no longer functions correctly.
A watchdog timer described in EP 1607864 could solve the stated problem. It is possible, however, that some of the transactions will not be detected or will be discarded, which may result in a loss of data.
Another approach, which is provided in GB 2313987, functions only when there is a system clock having a substantially higher frequency in the device, which may be used to oversample the SDA and SCL signals.